Day 4: Foundry and Advanced Packaging
Understanding why chip manufacturing and packaging — not just chip design — determine how many AI accelerators can reach the market.
Summary
AI chips do not appear out of thin air. Someone has to physically manufacture the silicon, then assemble multiple dies into a single high-performance package. That someone is overwhelmingly one company: TSMC. Today we study why the foundry and advanced packaging layers have become the tightest bottlenecks in the entire AI hardware supply chain — tighter, in many cases, than chip design itself. The key lesson: AI chip supply is a multiplication chain of design × fabrication × packaging × equipment, and a bottleneck at any single node constrains the entire output.
1) Why This Matters
In the AI hardware stack, most attention goes to chip designers like NVIDIA and AMD. But no matter how brilliant a GPU design is, it cannot reach the market unless a foundry can manufacture it and a packaging line can assemble it. Manufacturing and packaging set the hard ceiling on how many AI accelerators the world can actually use.
For investors, this means the real supply constraint often sits not with the designer, but with the manufacturer. Understanding foundry economics, packaging bottlenecks, and equipment dependencies is essential for reading AI hardware supply accurately.
2) One-Sentence Definitions
3) A Simple Analogy
Think of the AI chip supply chain as a construction project.
Fabless Designer (NVIDIA, AMD) = the architect who draws the blueprints
Foundry (TSMC) = the construction company that actually builds the structure
Advanced Packaging (CoWoS) = connecting multiple buildings into one high-speed campus
Yield = the completion rate — out of 100 buildings, how many pass inspection
EUV Equipment (ASML) = the only crane manufacturer in the world
4) Why Packaging Became the Real Bottleneck
The End of Monolithic Scaling
In the past, performance scaling came from shrinking transistors on a single die — classic Moore's Law. But physics has imposed hard limits. As dies grow larger, yield collapses because one defect kills the entire chip. The cost per transistor, which used to decline with each node, has started increasing at the most advanced processes.
The Chiplet Solution
Instead of building one massive monolithic die, designers now split functions across smaller dies called chiplets and connect them inside a single package. NVIDIA's Blackwell B200 places two GPU dies in one package, linked via NVLink-on-package. This is only possible because of TSMC's CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technology.
What CoWoS Actually Does
GPU dies and HBM dies are placed side-by-side on a silicon interposer — a thin layer of silicon containing thousands of TSVs (Through-Silicon Vias) that provide ultra-high-bandwidth die-to-die communication. This interposer is then mounted on a substrate. The result is a multi-die system that behaves like a single chip. The critical problem is that CoWoS packaging capacity is more constrained than chip fabrication itself. TSMC has been expanding CoWoS capacity aggressively, but demand from NVIDIA, AMD, Google, and Amazon continues to outpace supply.
What Beginners Often Get Wrong
People assume "chip shortage" means the fab cannot produce enough GPU dies. In the AI era, the more common bottleneck is packaging. The dies may already exist, but they cannot be assembled into functional products because CoWoS lines are full. This is why TSMC's CoWoS capacity expansion plans matter more to AI chip supply than wafer capacity alone.
5) The Process Node Race Still Matters
Advanced packaging is the hot topic, but process node competition remains vital. Each chiplet inside an advanced package is built on a leading-edge node. More advanced nodes deliver better power efficiency and compute density per die, which directly translates to better AI performance per package.
Each node transition increases manufacturing complexity and cost. A 3nm wafer is estimated to cost over $20,000. EUV lithography exposure steps multiply at each new node, driving up both time and expense. This cost structure is why foundry leadership has consolidated to TSMC — only they can reliably sustain the economics of leading-edge manufacturing at scale.
6) The Double Bottleneck: TSMC + ASML
TSMC — The Foundry Bottleneck
TSMC dominates both leading-edge chip fabrication and CoWoS advanced packaging. It controls two of the four factors in the AI chip supply equation. Its CapEx guidance, CoWoS capacity expansion timeline, and utilization rates effectively set the ceiling for global AI chip supply.
ASML — The Hidden Monopoly
Behind TSMC sits another monopoly. ASML is the sole supplier of EUV lithography systems. Its next-generation High-NA EUV tools, essential for 2nm and beyond, cost over $350M per unit with extremely limited annual output. TSMC's expansion speed is constrained by ASML's equipment delivery schedule.
This creates a double bottleneck structure: foundry capacity is gated by TSMC, and TSMC's own expansion is gated by ASML. Investors who track only chip designers are looking at demand signals while missing the supply constraints that actually determine output.
7) Who Matters at This Layer
8) Why Investors Should Care
The most common mistake in AI hardware investing is focusing only on chip designers. NVIDIA can design the best GPU in the world, but if TSMC cannot manufacture it and CoWoS cannot package it, that design never reaches the market. The real supply constraint sits in manufacturing and packaging.
The Core Framework
AI Chip Supply = Design × Fabrication × Packaging × Equipment
This is a multiplication chain, not an addition. A bottleneck at any single node constrains the entire output. TSMC controls two of these four factors (fabrication and packaging). ASML controls the equipment factor. Investors must track each node independently — looking only at NVIDIA tells you about demand, not about supply.
9) Connecting to the Stack
Day 1 → Day 4
The GPU dies from Day 1 are manufactured at TSMC on leading-edge nodes. Without the foundry, those designs are just files on a server.
Day 2 → Day 4
The HBM dies from Day 2 are placed next to GPU dies inside a CoWoS package. HBM's bandwidth advantage only materializes because advanced packaging connects HBM and GPU at extremely close range.
Day 3 → Day 4
NVLink interconnects from Day 3 begin at the package level. NVIDIA's NVLink-on-package connects multiple GPU dies within a single CoWoS package before extending outward to servers and racks.
Day 4 → Day 5
Once chips are fabricated and packaged, they go into servers and racks. Day 5 will cover how GPUs, memory, networking, cooling, and power come together in full AI systems.
10) What I Learned Today
- The foundry is the factory that turns chip designs into physical silicon, and TSMC dominates leading-edge manufacturing with over 90% share.
- Advanced packaging (CoWoS) assembles multiple dies into one high-performance system, and it is currently the tightest supply bottleneck in AI hardware — tighter than chip fabrication itself.
- AI chip supply is a multiplication of design × fab × packaging × equipment, with TSMC and ASML as the most irreplaceable nodes in the entire chain.
11) One Question I'm Still Thinking About
If Samsung and Intel eventually close the yield gap and offer competitive advanced packaging, how quickly could the TSMC concentration risk actually unwind — and what would that mean for pricing power across the foundry layer?
12) What Comes Next
In Day 5, I'll move from manufacturing to full system integration and study AI Systems, Servers, and Racks. Once we understand how chips are designed, connected, and manufactured, the next question is how they are assembled into deployable AI infrastructure — including OEMs, server builders, cooling, and rack-scale architecture.
Continue the AI Infrastructure Study Series
This series is designed to make the AI stack easier to follow — one layer at a time, from compute and memory to networking, packaging, and system economics.
Next: Day 5 — AI Systems, Servers, and Racks